To test traffic monitoring algorithms at very high speed, a synthesis traffic generator can prove useful.
Generating traffic at 10 Gb/s or more from a computer is hard. It is even almost impossible to saturate a 10 Gb/s link by sending small packets in software. This is why traffic generation devices are sold. But these commercial generators are very expensive.
I am developing an open-source architecture for an FPGA-based traffic generator. The code is available on GitHub. It is ready to use.
The hardware architecture is described in VHDL. A small piece of software in C is used for communication between the computer and the board, and a Python/Qt graphical interface helps configuring the generated traffic easily. The architecture is designed to be flexible and easy to extend with new features. It is described in this article.
FPGAs are chips that can be configured at very low level. They are much more efficient than processors for massively parallel computing, and for guarantying accurate processing delays. The traffic generator works with a board from INVEA-TECH, called COMBO-20G. It allows to send a precisely configured traffic (packet sizes, delays, contents) at a speed up to 20 Gb/s.
This traffic generator could also be used with an open NetFPGA 10G board to generate traffic up to 40 Gb/s. An adaptation of the code is required. I hope to be able to work on it soon.